The semiconductor field guide — from transistor to package

The simplest memory cell anyone has ever built. The capacitor either holds charge (a 1) or doesn't (a 0). The transistor is a gate that lets you read or write that charge. Called dynamic because the capacitor leaks — charge bleeds away in milliseconds, so the chip refreshes every cell every ~64 ms whether you use it or not.

Here's why DRAM scaling is harder than logic scaling: the capacitor needs to hold enough electrons to be reliably distinguishable from noise — around 30,000 per cell. As you shrink the cell, you have to keep that capacitance in a smaller footprint, which means making the capacitor taller and narrower. Modern DRAM capacitors are skyscrapers ~1.5 µm tall on a sub-transistor footprint. They're why DRAM fabs look different from logic fabs.

DRAM stopped using clean nm numbers years ago. The naming goes 1x → 1y → 1z → 1α → 1β → 1γ → 1δ — the "10nm-class" generations, half-pitches now ~14nm. Both Samsung and SK hynix use EUV at the leading DRAM node; Micron held out longer with DUV before adopting EUV in 2024.

Famously cyclical — boom-bust every 2–3 years. The consolidation to three players happened precisely because the cycle kept bankrupting smaller ones. China's CXMT is the new entrant, ~3–4 years behind on technology but ramping fast in volume.

NAND solved non-volatility with a clever trick: instead of a leaky capacitor, it uses a floating gate — a sliver of conductor completely surrounded by insulator, sitting inside the transistor. Push electrons onto it by tunneling them through the thin oxide and they're trapped there for years. The presence or absence of those electrons changes the transistor's threshold voltage, which is what you read.

The big shift came in 2013 when Samsung introduced 3D V-NAND. They stopped trying to shrink cells horizontally and started stacking them vertically. Each layer is built at coarse geometry (~40 nm — easy to manufacture), and density comes from how many floors you stack. Progression: 24 layers in 2013 → 64 in 2017 → 128 in 2020 → 200+ now → 400+ on roadmaps.

Modern NAND also stores multiple bits per cell by reading how much charge is on the floating gate, quantizing into 4, 8, or 16 levels:

Samsung ~33% · SK hynix + Solidigm ~22% · Kioxia ~19% · Micron ~14% · Western Digital ~10% · YMTC uses a clever Xtacking architecture — periphery logic and memory array on separate wafers, then bonded together. Sanctioned but still shipping.

Look at a B200 GPU and ask what's expensive. Roughly half the package by area, and a similar share by cost, isn't the GPU. It's eight towers of HBM next to it. A standard DDR5 stick gives you ~50 GB/s. A single HBM3E stack gives you ~1.2 TB/s. 24× the bandwidth, 1/100 the footprint, 1/3 the power per byte moved. How?

The trick is brute-force parallelism. A regular DRAM chip talks to the world through ~64 wires running fast. An HBM stack talks through ~1,024 wires running slower. Total bandwidth is pins × speed, and HBM wins on pins by a huge margin. But you can only fit 1,024 wires between two chips if they're millimeters apart. That's the whole reason CoWoS exists: to give you a silicon surface flat enough and wired finely enough to land 1,024 connections per stack.

The stack itself is 8 to 12 DRAM dies bonded vertically with TSVs (through-silicon vias — copper wires drilled through the silicon), sitting on a base die that handles I/O. SK hynix is now making custom base dies tailored to specific customers — that's how deep into vertical integration HBM has pushed.

SK hynix was first to qualify HBM3E with NVIDIA. Micron is the second source NVIDIA cultivated to avoid SK hynix monopoly pricing. Samsung has had qualification problems through 2024–25 and is fighting to catch up.

The math that makes HBM the real story of the AI era: a modern LLM inference workload is dominated by memory bandwidth, not compute. Reading model weights from memory once per token sets the speed limit. A B200 with 192 GB of HBM3E at 8 TB/s aggregate can serve a 100GB model at maybe 80 tokens/sec per stream. Without HBM, it'd be 5. The GPU is fast because the memory next to it is fast — not the other way around.

For thirty years there's been a pitch: a single memory technology that combines DRAM speed with NAND non-volatility. Several have shipped. None have replaced anything.

The honest summary: the memory hierarchy has been remarkably stable for 25 years (registers → SRAM cache → DRAM → SSD) and probably will be for another decade. Emerging memories chip away at the edges, but the established types keep getting cheaper faster than the new ones can.

In the 1990s, moving a bit one millimeter on-chip cost about as much energy as a logic operation. Today, a 64-bit fused-multiply-add costs ~25 pJ. Moving that result across a die: ~10 pJ. Off-die through HBM: ~200 pJ. Across a rack: ~1,000 pJ. Across a data center: ~10,000 pJ. Compute got cheaper much faster than wires did — and that's the deepest reason the industry pivoted to packaging and chiplets.

Inside a single die, transistors are connected by 15–20 stacked layers of copper wires called the back end of line (BEOL). Bottom layers are tiny (~30nm pitch, matching transistor scale) and run short distances. Each layer up is wider, taller, and runs farther. The very top layers carry power and clocks across the whole chip.

Two things matter about BEOL. First, it's roughly half the height of the chip — transistors live in the bottom 1µm; the wires occupy 5–10µm above. Second, it hasn't scaled like the transistors did. Wire pitch shrank ~2× over a decade while transistor density grew 10×. Increasingly the bottleneck on a chip is finding room for the wires between the transistors. This is part of why backside power matters: moving power rails to the bottom of the silicon frees up the top wiring for signals.

When you split a chip into chiplets, you need them to talk almost as fast as on-die wires. UCIe (Universal Chiplet Interconnect Express) is the new industry standard — what USB or PCIe were for their tiers, an open spec so a chiplet from one vendor can plug into a package from another. Backed by Intel, AMD, Arm, TSMC, Samsung, Google, Meta, basically everyone except NVIDIA. Today: 16–32 GT/s per lane; roadmap 64+ GT/s.

UCIe is a protocol — it specifies how dies talk. The physical interconnect is whatever the package gives you. As physical density rises, the line between "two chips" and "one chip" blurs:

Outside the package but on the same board, the dominant standard is PCIe. Every CPU, GPU, NVMe, and NIC speaks it. Each generation doubles bandwidth: PCIe 3 (8 GT/s, 2010) → 4 → 5 (32 GT/s, current servers) → 6 (64 GT/s, shipping 2025) → 7 (128 GT/s, 2027+).

For GPU-to-GPU specifically, PCIe is too slow. NVIDIA built NVLink as a parallel proprietary fabric just for this. Watch the difference:

NVLink is what lets 8 GPUs in a server act as if they were one giant GPU with 8× the memory. Without it, splitting a trillion-parameter model across multiple GPUs would be impractically slow. Above NVLink sits NVSwitch, NVIDIA's switch chip that lets every GPU in a rack talk to every other GPU at full NVLink speed simultaneously.

The competing standards: AMD Infinity Fabric (one generation behind), UALink (open standard launched 2024 by AMD/Intel/Broadcom/Cisco/Google/Meta/Microsoft — the "anyone but NVIDIA" alliance, first products 2026), and scale-up Ethernet with Broadcom Tomahawk. Whether UALink can build a credible alternative ecosystem before NVLink lock-in becomes total is the strategic question.

Once you've packed 8 or 72 GPUs into a rack with NVLink, you connect racks to each other with traditional networking. Two protocols dominate: InfiniBand (lower latency, NVIDIA-owned via Mellanox) and Ethernet (universal, cheaper, hyperscaler-preferred to avoid lock-in). Current speed grade: 400 Gb/s, with 800 Gb/s rolling out 2025–26 and 1.6 Tb/s on roadmaps for 2027+.

The Ultra Ethernet Consortium (AMD, Broadcom, Cisco, HP, Intel, Meta, Microsoft, Oracle) is taking Ethernet and making it as good as InfiniBand for AI. UEC 1.0 spec landed 2025; products 2026. This is the layer where Broadcom quietly makes a fortune — their Tomahawk and Jericho switch chips run most of the world's AI Ethernet fabric. Tomahawk 6 (2025) hits 102.4 Tb/s per chip.

Beyond a few meters, copper runs out of steam. The signal degrades, the cable thickens, the SerDes burns too much power. So you switch to light, with optical transceivers at each end. Today these are pluggable modules; the next generation embeds them inside the chip package itself.

The frontier beyond CPO: on-package optics for chip-to-chip — using light to connect GPUs to each other or to memory directly, replacing copper of NVLink. Three startups to watch: Ayar Labs (silicon photonics chiplets, NVIDIA-backed), Lightmatter (passive photonic interposer "Passage"), Celestial AI (Photonic Fabric). None has shipped at hyperscale yet. If one does, it could be a bigger architectural shift than the move to chiplets.

Robert Dennard at IBM showed in 1974 that if you shrink every dimension of a transistor by a factor of k, you can drop the operating voltage by k too — and power per area stays constant even though you've packed k² more transistors in. From the Intel 4004 (740 kHz, 1971) to Pentium 4 (3.8 GHz, 2005), clock speeds rose nearly 5,000×. Free lunch.

Then around 90nm, voltage scaling stopped. The reason is gate-oxide leakage: as you make the insulator under the gate thinner, electrons start tunneling through it even when the transistor is supposed to be off. Below a certain thickness, "off" current becomes a sizable fraction of total power. Voltage stuck around 1V and has barely moved since. Every node packs more transistors at roughly the same voltage — so power density goes up every generation. A modern leading-edge die runs at ~1W per mm² in active areas — the heat flux of a kitchen stove, just smaller and concentrated.

Power on a chip splits into two pieces. Dynamic power is energy spent flipping bits — every transistor switch costs ½CV²f joules. Half of all chip design optimization is reducing one of those three knobs. Static power is leakage — current that trickles through a transistor even when it's "off." Twenty years ago this was a rounding error; on a 3nm chip it's roughly a third of total power.

Dynamic power scales linearly with frequency, but you need more voltage to clock faster, and dynamic power scales with V². Push frequency 30% higher and you might pay 60–100% more power. This is why modern chips don't really run faster generation-over-generation; they spread work across more cores at lower clocks instead. It's also why Apple, AMD, and now Intel ship heterogeneous CPUs: efficiency cores at low voltage for background work, performance cores that wake up only when needed.

A modern AI chip operates at ~0.7V — lower than a flashlight battery — but draws ~1,200 watts. By Ohm's law that's ~1,700 amps of current flowing into a piece of silicon roughly the size of a postage stamp. A household circuit breaker trips at 15 amps. A car starter pulls maybe 250 amps for a moment. A B200 GPU pulls 1,700 amps continuously.

Getting that current into the chip is its own engineering problem. The current arrives at the package via thick copper traces, gets distributed across the substrate, then climbs up through the chip's wiring stack to reach transistors at the bottom. Every step has resistance. Every step drops voltage. By the time current reaches a transistor, the voltage might have sagged from 0.75V to 0.72V — a 4% droop that meaningfully affects switching speed.

This is why backside power delivery matters more than its understated marketing suggests. Today, power and signals fight for the same wiring layers from the top side. With BSPD (Intel PowerVia, TSMC at A16), you flip the wafer and put power rails on the bottom of the silicon, separate from signal routing. The signal layers on top get more room. Power gets to transistors more directly. Performance bumps of ~5–8% are typical.

A B200 GPU dissipates ~1,200W. A Grace-Blackwell superchip dissipates ~2,700W. An NVL72 rack with 72 GPUs dissipates ~120 kW. That's about 60 home microwave ovens running continuously, in one rack-shaped box. Most existing data centers were designed for ~10–15 kW per rack. AI broke that.

The transition matters because cooling capability now dictates compute capability. You can buy more GPUs than you can cool. Operators with liquid-cooled facilities can run dense racks; operators stuck on air can't. Microsoft, Meta, Google, Amazon are all racing to retrofit. There's also a water angle — a hyperscaler-scale data center can consume millions of gallons per day for evaporative cooling, which has become a serious community/regulatory issue in places like Arizona and Spain.

Heat doesn't spread evenly. A GPU running a kernel might have 90°C in active SM tiles and 60°C in idle areas. When you stack two compute dies vertically, the bottom one becomes a thermal prison — heat from both has to escape through the same path.

This is why hybrid bonding for compute dies (vs cache) is so hard. AMD's 3D V-Cache works because the cache layer doesn't draw much power — bottom die stays cool. CFET stacks transistors at the device level — even worse. Cooling solutions for 3D logic don't exist yet at scale. The whole 3D logic roadmap depends on solving this, with microfluidic cooling (etching channels into the silicon itself) as the leading candidate.

One of the cleverest knobs in modern AI hardware is what kind of number you compute with. A 32-bit float is precise but slow; a 4-bit number is imprecise but eight times denser and faster. The realization driving the last decade: neural networks don't need much precision — they're noisy by nature, and small numerical errors get averaged out across billions of operations.

A B200's headline number is 20 PFLOPS at FP4. The same chip in FP16 is ~1.25 PFLOPS — sixteen times less. Both numbers are real; they just describe different workloads. When you read a benchmark, the format matters as much as the number. The B200 vs H100 jump is partly silicon improvement, partly just dropping from FP8 to FP4. Models are trained at higher precision and then quantized down for serving — GPTQ, AWQ, SmoothQuant are the tools that make this work.

NVIDIA's hardware lead is real but maybe 6–12 months. The software lead is ~5 years and growing. CUDA is a stack — every layer optimized over 18 years, every layer assumed by every paper, model, tutorial, and open-source library. To displace it, AMD needs not just competitive hardware but competitive every layer of the stack, plus migration tooling, plus enough early customers for ecosystem effects.

The one place ROCm is winning is at the absolute top end. AMD's MI300X has more memory than H100 (192GB vs 80GB), so for the very largest models — 405B-parameter Llama, GPT-class — it can be the right hardware regardless of software friction. This is the wedge AMD is exploiting. For everyone else, CUDA still wins by default.

You now have the framework to read any modern AI chip announcement. When a spec sheet says "5 PFLOPS FP8, 192 GB HBM3E, 8 TB/s memory bandwidth, 1.8 TB/s NVLink, 1,000W", here's what each number actually means:

The interplay between these numbers IS the chip. Great FLOPS but weak memory bandwidth = bad at inference. Great memory bandwidth but weak interconnect = bad at large-model training. Reading the balance tells you what the chip is for.

The phrase "leading-edge" matters. China makes huge volumes of automotive chips at 28nm; the US has Intel and GlobalFoundries running older nodes; Korea has Samsung. But for the actual frontier — chips that train Llama, run B200 GPUs, power iPhones — there is essentially one place. And within that place, essentially one company.

This is the result of three decades of compounding advantages. TSMC pioneered the pure-play foundry model — they only make chips for other companies, never compete with their customers. That gave them economies of scale beyond what any IDM could match. Their Hsinchu fab cluster has thirty years of accumulated process knowledge: cleanroom layouts, thin-film recipes, trained workforce, supplier relationships. None of this is replicable in the timeframe of a five-year geopolitical crisis.

The phrase Silicon Shield describes the strategic reality: Taiwan's chip dominance is, paradoxically, what protects it. A Chinese invasion or blockade would catastrophically disrupt global semiconductor supply, recessing the world economy and triggering a response from the US, Japan, and Europe so severe that even Beijing's hawks pause. The shield works only as long as Taiwan remains the unique source. Once it isn't, the shield is gone. Almost everything in chip geopolitics flows from this calculation.

No country has a complete supply chain. The US has design tools and a few fabs but no leading-edge chemicals or lithography. China has the chemicals capacity and lots of mature-node fabs but no leading-edge lithography or design tools. Europe has ASML but no fabs at scale and weak design. Japan has the materials and tools but exited fabs years ago. Taiwan has the fabs and packaging but everything else flows in.

This web is a feature, not a bug — at least it was. After WWII the chip industry naturally distributed because comparative advantage and free trade drove specialization. The result is a system that works perfectly when everyone cooperates and breaks catastrophically when they don't. Every export control, every tariff, every supply chain "decoupling" is a force trying to convert what was a feature into a fault line.

EUV lithography systems alone are ~$200M each, and a leading-edge fab needs 10–20 of them. The cleanroom standards for 2nm are vastly stricter than for 28nm — class-1 air, vibration isolation requiring foundations decoupled from the surrounding earth. The mask shop alone might cost $1B. Tens of billions before you produce a single wafer.

The economic consequence is brutal: only TSMC, Samsung, and Intel can afford to play at the leading edge. Everyone else either licenses, partners with, or gives up. Even SMIC, with massive Chinese state backing, isn't realistically catching up — they're trying to do it without EUV and getting 20–40% yields. There is no fourth competitor on the horizon.

This is also why the TSMC Arizona fab matters and why it's been so hard. Construction costs are 4–5× Taiwan's. Workforce shortages, regulatory friction, supply chain mismatches — all the reasons the chip industry concentrated in Taiwan in the first place are reasons it can't easily be unwound. The fab opening was originally targeted for 2024–2025; it's now 2028.

The most consequential event was October 7, 2022 — the Biden BIS rules. Leading-edge chips and chipmaking equipment got blocked at the border. ASML couldn't sell EUV machines to China; even some DUV systems were restricted. NVIDIA had to design H800, A800, then H20 — China-specific cut-down GPUs that kept FLOPS below thresholds. China responded with the Big Fund III, accelerated SMIC investments, and a focused push on Huawei's Ascend chips.

Then came the 2025-26 reversal. The second Trump administration shifted the playbook. Tariffs replaced subsidies as the preferred mechanism. A 25% tariff on advanced AI chips like the H200. The US government took a ~10% stake in Intel — striking departure from American policy norms. NVIDIA and AMD now pay 15% of their China chip revenue to the US Treasury. Most consequential: the BIS rule change that moved the H200 from "presumption of denial" to "case-by-case review" for export to China — partial reopening of a market the previous administration had tried to close.

Internal critics, including former first-term Trump officials, argue this hands China a multi-year head start. Defenders argue tariffs and revenue capture do the same job as bans without forfeiting US share. Either way, the strategic posture has shifted from denial to transactional.

The early evidence is mixed. The US CHIPS Act funded TSMC's Arizona expansion, Intel's Ohio fab, Samsung Texas, and various Micron projects. Construction is happening — slower and more expensive than promised. EU progress is even slower; Intel's planned Magdeburg fab in Germany was paused. The 20% global share goal looks unreachable. China's mature-node capacity is growing fast (worrying Western producers about 28nm oversupply), but it's not closing the leading-edge gap in any near-term timeframe.

The honest read: every major economy is hedging. Each country wants to make sure it isn't left holding nothing if the global supply chain fractures. The total spending is duplicative — the world doesn't actually need five TSMCs — but no one wants to be the country without a backup.

A modern internal combustion car contains 1,500–3,000 chips. An EV has 3,000–5,000. A new iPhone has roughly 30. A hospital MRI has thousands. A weather satellite has thousands. The smart electric meter on your house has dozens. None of these are leading-edge.

This is also why the post-COVID chip shortage was such a shock — it wasn't about AI chips, it was about $1–5 microcontrollers used in car door modules. By 2022, factories worldwide were idle waiting for $0.50 chips. The trailing edge is invisible until it stops working.

The Tesla Model 3 was the watershed: in 2017, Tesla switched its main inverter to a SiC module from STMicroelectronics. That single product validated SiC for mass-market automotive and triggered a billion-dollar investment wave from Wolfspeed, Infineon, ON Semi, ROHM, and others. Today, leading-edge EVs almost universally use SiC.

GaN is following a similar arc on a different timescale. GaN excels at high-frequency switching, which means smaller transformers and capacitors. The 100W laptop charger that's a third the weight of last decade's? GaN. Datacenter 48V → 0.7V conversion stages? Increasingly GaN. At hyperscaler scale the efficiency gains are hundreds of millions of dollars per year.

The geography is shifting. China is building enormous SiC and GaN capacity — both substrates and devices. Wolfspeed (the SiC substrate leader) is in financial trouble after over-investing during the EV bubble. Chinese SiC suppliers now produce ~30% of world wafer capacity. If you wanted to identify a part of the chip industry about to be dominated by Chinese manufacturers, power semiconductors is a good candidate.

Sony makes ~50% of all smartphone image sensors. Samsung is second at ~20%. OmniVision third. Sony's lead is real — they pioneered the stacked CMOS sensor, which is structurally what HBM is for memory: pixels on top, logic on a separate die underneath, TSVs between. Newer sensors stack three layers — pixels / DRAM / logic — for global-shutter capture and on-chip object recognition before data even leaves the sensor.

There is no Moore's Law for image sensors. Just continuous incremental refinement of pixel size, quantum efficiency, color filter dyes, microlenses, on-chip processing — accumulating over decades. A 2026 iPhone sensor isn't 100× better than a 2010 sensor. It's maybe 5–10× better, and that's incredibly hard-won.

Most MEMS fabs are old — 200mm wafers, processes from the 1990s, but with extremely refined recipes. The barrier to entry isn't the equipment — it's the recipe. You can't just buy MEMS tools and start making accelerometers.

Most automotive chips come from specialists: Infineon (largest), NXP, STMicro, Renesas, ON Semi, TI. They run their own fabs at mature nodes with extreme reliability requirements — a car chip has to work for 15 years through temperature swings, vibration, and corrosion. Qualification cycles are years long. Margins are stable but unspectacular. The business is consistent and durable in a way leading-edge logic isn't.

By some estimates, China will add more 28nm-and-above capacity in 2024–2027 than the rest of the world combined. The leading-edge sanctions don't apply — this isn't 5nm. It's exactly the nodes that build automotive chips, power management, image sensors, communications. The CHIPS Acts everywhere are about leading edge. The actual capacity wave is at trailing edge.

When China's mature-node capacity comes online, prices of those chips could fall sharply. Western automotive chip makers — Infineon in Germany, NXP in the Netherlands, ST in France/Italy, TI in the US — have to figure out how to compete with subsidized Chinese capacity that doesn't need to make a normal return. This is a slow-motion crisis that gets less press than AI chip wars but probably matters more for the long-term health of US and European chip industries.

One of the most counterintuitive things about chips: mature doesn't mean commoditized. A 180nm BCD power process at TI or Infineon is just as defensible as TSMC's 2nm — the moat is just a different shape. At leading edge, the moat is capex and process know-how that takes 20 years to accumulate. At mature, the moat is customer qualifications that take 5 years to win, decades of accumulated design libraries, and product lifecycles measured in decades. Nobody is trying to disrupt the 180nm BCD business because the customers don't want to be disrupted.

Read this top-to-bottom and a structure emerges. The leading edge is a monopoly — TSMC has 90%+ at 3nm, and the moat is thirty years of process accumulation plus capex no one else can match. 5nm and 7nm are an oligopoly — TSMC + Samsung + (at 7nm) SMIC and Intel. 14nm down to 22nm becomes contested — four to six foundries, healthy margins, real competition. 40/65nm is diverse — eight or more foundries each holding their share. 90/130/180nm flips the model entirely — these aren't pure-play foundry markets; they're IDM territory where companies like Infineon, TI, NXP run their own fabs and don't sell to outsiders.

The 180nm moat is invisible from the outside. An IDM like TI has tens of thousands of part numbers, each qualified into customer products that have 20-year lifecycles. The fab process recipes encode 30+ years of accumulated tweaks. The customer engineers at Bosch or John Deere have spent careers learning that specific TI part's behavior at temperature extremes. Even if a competitor offered the same chip at half the price, the qualification cost on the customer side would dwarf the savings.

The node ladder above is for CMOS logic — the same kind of transistors used in CPUs, GPUs, and MCUs, just at different feature sizes. But large parts of the chip industry don't use CMOS logic at all, or use it as a layer alongside something else. These are specialty processes, and they have their own player ecosystems entirely separate from the foundry world.

Each of these is its own world, with its own dominant suppliers, its own process physics, its own customer base, and its own competitive dynamics. Sony has been the world's #1 image sensor maker for 15+ years. Bosch has been the world's #1 automotive MEMS maker for 25+ years. The Samsung-SK Hynix-Micron triopoly in DRAM has been stable for over a decade. None of these positions are being seriously challenged.

And this is what makes the chip industry so much wider than people realize. There isn't a chip industry. There's the leading-edge logic industry. The mature foundry industry. The IDM analog industry. The DRAM industry. The NAND industry. The image sensor industry. The MEMS industry. The power semi industry. The compound semi industry. The photonics industry. Each operates by different rules. Each has its own moats. Each has its own geopolitical dynamics.

When someone says "the chip industry," ask which one. The answer changes everything that follows.

Five categories matter: photonic interconnect (already shipping), photonic compute (early commercial 2026), neuromorphic (edge AI now, mainstream by 2027), in-memory analog compute (mid-decade), quantum (advantage by ~2026, fault tolerance ~2029-30, real impact later), and 2D materials and exotic semiconductors (still labs). Each gets a section. None will replace silicon for general-purpose compute soon — they will displace it for specific workloads where they have clear physical advantages.

Photonics is two stories, not one. Photons moving data — chip-to-chip, rack-to-rack, building-to-building — is decisively winning. Long fiber runs in datacenters have been optical for decades. What's new is optics moving inside the package itself: co-packaged optics (CPO). NVIDIA's Spectrum-X and Quantum-X switches, shipping late 2025 into 2026, integrate optical engines directly with the switch ASIC, removing the pluggable transceiver entirely. Power per bit drops ~3-4×. Photons computing data is the harder, separate story. Both use the same materials and similar fabrication, but they're not the same problem.

Three material platforms compete: silicon photonics (SiPh) — leverages CMOS infrastructure, dominant for transceivers. Indium phosphide (InP) — best for lasers and high-power optical sources. Silicon nitride (SiN) — ultra-low loss, good for passive routing. Thin-film lithium niobate (TFLN) — emerging for high-speed modulators (Q.ANT's compute play). TSMC's silicon photonics offering went into volume in 2024-25; the photonics fab is now a real business.

The CPO transition matters strategically. Pluggable transceivers are a $12B+/year market. Companies like Coherent, Lumentum, InnoLight dominate transceivers. CPO threatens that ecosystem because the optics live inside the switch package now — the transceiver vendors get displaced unless they pivot. Meanwhile, switch silicon designers (Broadcom Tomahawk, NVIDIA Spectrum) absorb the optics business. This is the largest unsung supply-chain restructuring of the AI era.

The case for computing with light: a beam of photons passing through a Mach-Zehnder interferometer can perform a multiplication essentially for free, at the speed of light, with negligible energy. Stack many of these and you have a matrix multiplier — exactly the operation AI workloads need most. Lightmatter, Q.ANT, Celestial AI, Lightelligence, and others have working photonic matrix multipliers shipping (early 2026) or in development.

The catches:

1. Precision. Photonic compute is fundamentally analog. You can't easily get more than 4-8 bits of precision out of an interference pattern. That's fine for inference (FP4/INT8 territory), bad for training (FP16+ usually needed). Most photonic compute startups are inference-only as a result.

2. Nonlinearity. Neural networks need nonlinear activations (ReLU, GeLU). Light is naturally linear. Most photonic accelerators do the linear ops in light, then convert to electrical for the nonlinearity, then back. Each conversion costs energy and latency. Pure-photonic compute would need on-chip optical nonlinearity, which remains a research problem.

3. Memory. Light is fundamentally a flow, not a store. There is no "photonic RAM." Weights still have to be loaded from DRAM via electrical interfaces, then converted to phase-shift settings, then held there. The von Neumann bottleneck doesn't disappear — it shifts.

Despite all this, photonic compute is real and shipping. Q.ANT's NPU launched H1 2026 in collaboration with the Jülich Supercomputing Centre, using thin-film lithium niobate. Lightmatter has working systems. Celestial AI is building photonic fabric for AI clusters. The bet isn't that photonics replaces GPUs — it's that for some specific workloads (transformer inference, optical neural networks for sensor processing) it offers 10-100× efficiency gains while being just barely good enough.

The brain runs on roughly 20 watts. A B200 GPU running similar tasks (image recognition, real-time inference) runs on 1,200. The factor of 60× isn't because brains have better silicon — it's because they compute fundamentally differently. Spiking neural networks only fire when there's information to communicate (sparse, event-driven), and memory and compute are colocated (no von Neumann bottleneck).

Neuromorphic chips try to capture both properties on silicon. Intel Loihi 3, commercial release January 2026, has digital implementations of spiking neurons with on-chip learning. IBM NorthPole, in production for 2026, takes a different approach: co-locate memory directly with compute units, eliminate the off-chip DRAM bus, achieve up to 25× the energy efficiency of an H100 for image recognition. BrainChip Akida is the commercial edge leader, shipping in real products since 2023.

The catch is software. Loihi and NorthPole don't run PyTorch out of the box. Spiking neural networks require training and deployment in spike encodings — temporal patterns of binary events rather than dense floating-point activations. Tools have improved (Intel's Lava framework, IBM's NorthPole SDK) but it's a different mental model. Most ML engineers have never written a spiking model.

Where neuromorphic wins clearly: edge AI with hard latency or power constraints. AR glasses where battery life is everything. Robotics that need sub-millisecond reaction. Always-on sensor processing where the device sleeps until something interesting happens. Mercedes and BMW are reportedly integrating neuromorphic vision into autonomous braking. It's not replacing the datacenter GPU. It's filling a category the datacenter GPU was never well suited for.

Every architecture we've covered moves data: from HBM to compute, from registers to ALUs, from cache to cores. Each move costs energy. The end-state of "moving data is the bottleneck" is the realization that you shouldn't move it at all. Compute should happen inside the memory.

Three technologies pursue this:

ReRAM (Resistive RAM). Memory cells whose resistance can be set to many values, not just 0 or 1. Apply a voltage, read the current — by Ohm's law, current = voltage × conductance. If conductance encodes a weight, then a single ReRAM crossbar performs a matrix-vector multiply analog-style, in a single physical step. No clock cycles, no data movement. Companies: Mythic AI, Crossbar, Weebit Nano.

PCM (Phase-Change Memory). Cells made of chalcogenide alloy whose crystal/amorphous state encodes data. IBM has built PCM-based analog accelerators that achieve 10-100× efficiency on transformer workloads. Same principle as ReRAM: use the device physics itself as the multiplier.

Ferroelectric (FeFET). Transistors whose threshold voltage shifts based on a ferroelectric layer's polarization. Non-volatile, fast-switching, integrate well with CMOS. The "what if NAND flash and SRAM had a child" technology. Several startups; major players (TSMC, Imec) have R&D programs.

The performance numbers are wild. Mythic's M1076 analog matrix processor claims 25 TOPS at ~3W — order-of-magnitude better than digital equivalents. IBM's analog AI work has shown ~14× efficiency improvements over GPUs for transformer inference.

The catches are equally serious:

Precision. Analog computation accumulates noise. ReRAM cells drift over time. Most in-memory analog accelerators top out at 4-8 bits effective precision. Inference only.

Programming. Each weight has to be carefully written into a memory cell with precise resistance. Slow, sometimes destructive (PCM cells wear out after ~10⁹ writes). Models are loaded once and run for a long time.

Process integration. ReRAM, PCM, and FeFET all require materials and processing steps that don't exist in standard CMOS fabs. Mass production requires retooling, which limits scale until volume justifies it.

Mid-decade is the realistic timeframe. If Taalas's mask-ROM approach is the most extreme version of this idea, in-memory analog is the more flexible (but slower-to-program) cousin. The two together represent a serious challenge to the GPU-plus-HBM model — the kind of challenge that's invisible until it's not.

Quantum computing has been "five years away" for decades. The reason it's no longer a pure punchline is that the milestones have actual dates now. IBM's roadmap is the most concrete: Loon (2025) demonstrated qLDPC building blocks. Kookaburra (2026) is the first QEC-enabled module — quantum memory and logic combined. Cockatoo (2027) connects modules. Starling (2029) — the target of the whole roadmap — runs 100 million quantum gates on 200 logical qubits. That's the regime where quantum computers can do things classical machines cannot.

The honest assessment of quantum in 2026: we are right at the inflection between "interesting research" and "experimentally useful." Verified quantum advantage — beating classical computers on a problem people care about — is plausible by year-end 2026. Useful quantum computing for real applications (chemistry, materials, optimization) requires logical qubits with low enough error rates to run long algorithms. That's the Starling 2029 milestone. Even Starling at 200 logical qubits won't break RSA encryption (which needs ~4,000+ logical qubits at much lower error rates).

Three competing platforms. Superconducting qubits (IBM, Google) — most mature, requires near-absolute-zero cryogenics. Trapped ions (Quantinuum, IonQ) — slower but better fidelity, easier connectivity. Photonic (PsiQuantum, ORCA) — operates at room temperature, scales differently, harder to do gates. Topological (Microsoft) — Microsoft's bet that exotic Majorana fermion qubits will be inherently error-corrected. Still mostly research.

What quantum computing won't do, even in 2030: replace your laptop. Solve general AI. Crack encryption tomorrow. It will probably be useful for specific problems with quantum structure — molecular simulation, certain optimization classes, quantum chemistry — where the speedup is exponential and the problems are otherwise intractable.

Silicon CMOS still has 5-10 years of meaningful scaling left through CFET, backside power, and packaging. But the long-term question is what happens past atomic limits. The leading candidates are 2D materials — atomically thin sheets that can act as semiconductors with much better electrostatics than 3D silicon at extreme scales.

The honest read: none of these will replace silicon for general-purpose logic in the 2020s. Possibly not in the 2030s either. But the same was true of FinFET in 2000 and EUV in 2010. The transition from "lab" to "production" takes 15-25 years even when the material is well-understood. What matters is which 2D material's manufacturing processes mature first, and what specific niches they win before they win general logic.

Backside power, CFET, advanced packaging, and the AI-specific architectural moves we covered in earlier sections will carry mainstream silicon through 2030 and possibly to 2035. After that, the field branches: photonics for some workloads, neuromorphic for others, in-memory analog for a third, quantum for a fourth, and exotic materials for whatever's left at the bottom of the transistor stack. "The chip industry" stops being one industry.

A bare 300mm wafer costs ~$100. About $90 of that is the polishing — Sumco and Shin-Etsu polish to atomic flatness, RMS surface roughness <0.1nm. The wafer surface is one of the flattest things humans manufacture.

The fab step (#6) is where the bulk of the time and cost concentrates: 1,000–1,500 individual process steps over 3–4 months. Lithography, etch, deposition, ion implant, planarization, inspection, repeat. Each step is a chance for a defect that ruins the chip.

The cleanroom is organized in bays — each bay holds equipment for a specific process type. Wafers move between bays inside FOUPs (Front Opening Unified Pods), sealed plastic carriers that hold 25 wafers each. FOUPs travel along ceiling-mounted rails — Overhead Hoist Transport — that thread through the cleanroom like a model train system.

People wear bunny suits because humans shed five million skin particles per minute. Modern fabs are increasingly automated; TSMC's most advanced fabs have entire wings that operate without staff inside during normal operation. The yellow light is because UV would expose photoresist.

The mask itself is made by an electron beam writer — a multi-million-dollar machine that draws the pattern one pixel at a time, taking 8–24 hours per mask. EUV masks are an order of magnitude more delicate than DUV due to their multilayer molybdenum/silicon reflectors. A speck of dust on the mask would print as a defect on every chip on every wafer — which is why pellicles exist, even though EUV pellicles remain technically extremely difficult.

Only a handful of mask shops can do leading-edge work: TSMC's internal mask shop, Samsung's, Intel's, plus merchant suppliers Photronics (US) and Toppan and DNP (Japan). Mask shop queue time can affect tape-out schedules. For all the talk of EUV scanners, the mask shop is its own bottleneck.

Photoresist for a leading-edge fab has to be cleaner than almost any liquid on Earth. Particulate counts under 5 nanometers are tracked. Metal contamination is measured in parts per trillion. The factories that make this stuff are themselves cleanrooms.

JSR engineers work alongside TSMC engineers on every new node. The qualification cycle for a new resist on a new node is 18–24 months. A new entrant doesn't just need to make the chemicals; they need to convince TSMC to spend two years qualifying them. Japan's photoresist position is the chip industry's most underappreciated chokepoint — and it's why Japanese export controls on photoresist (briefly imposed on Korea in 2019) caused a global chip industry panic.

Identifying yield killers requires inspection — every wafer is inspected at multiple steps. Statistical analysis correlates defects with specific tools, recipes, even individual machines. Engineers track yield down to specific FOUPs and identify root causes. The deepest moat in fab manufacturing is institutional knowledge of yield improvement. TSMC has been doing this for thirty years across thirteen process generations. The accumulated playbooks — which tools tend to drift, which materials degrade in storage, which inspection metrics correlate with which yield killers — exist nowhere else.

This is also why Intel's manufacturing struggles have been so hard to reverse. They had the playbooks once. Stumbling at 10nm in the late 2010s broke their cadence; restarting requires both fresh capex and rebuilding institutional muscle that atrophied. Samsung is in a similar place with leading-edge yields — they have the equipment but not the consistent yield outcomes TSMC produces.

Below these six, hundreds of smaller specialists: Hitachi High-Tech, Lasertec (Japan, EUV mask inspection), Advantest and Teradyne (testing), Ebara (CMP and pumps), SCREEN (wet), Axcelis (implant), Onto Innovation (inspection), AIXTRON (Germany, MOCVD). Each leading-edge fab uses tools from 50+ different equipment companies.

The trade-control implications are clear: blocking ASML EUV doesn't only block the ~$200M scanner. It indirectly blocks all the upstream Japanese and US tools co-designed around EUV processes. The supply chain isn't a chain — it's a mesh. Cutting any leading-edge fab off from ASML cuts it off from the entire ecosystem of tools that have been jointly engineered around EUV's process windows.